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1、1.中断号定义typedefenumIRQn(/*Cortex-M4ProcessorExceptionsNumbers*/NonMaSkabIemJIRQn=-14,*!2NonMaskableInterrupt*/MemoryManagementJRQn=-12,*!4Cortex-M4MemoryManagementInterrupt*/BusFauItJRQn=-Ilz*!5Cortex-M4BusFaultInterrupt*/UsageFauItJRQn=-IOz*!6Cortex-M4UsageFaultInterrupt*/SVCaIIJRQn=-5z*!11Cortex-M4
2、SVCallInterrupt*/DebugMonitorJRQn=-4,*!12Cortex-M4DebugMonitorInterrupt7PendSVJRQn=-2,*!14Cortex-M4PendSVInterrupt*/SysTick_IRQn=-1,*!15Cortex-M4SystemTickInterrupt*/*STM32specificInterruptNumbers*/WWDGJRQn=O,*!WindowWatchDogInterrupt*/PVDJRQn=1,*!PVDthroughEXTILinedetectionInterrupt7TAMP_S7AMP_IRQn
3、=2,*!TamperandTimeStampinterruptsthroughtheEXTIline*/RTC_WKUP_IRQn=3,*!RTCWakeupinterruptthroughtheEXTIline*/FLASHJRQn=4,*!FLASHglobalInterrupt*/RCCJRQn=5,*!RCCglobalInterrupt*/EXTIOJRQn=6,*!EXTILineOInterrupt*/EXTIlJRQn=7,*!EXTILinelInterrupt*/EXTI2JRQn=8,*!EXTILine2Interrupt*/EXTI3JRQn=9,*!EXTILin
4、e3Interrupt*/EXTI4_IRQn=10,*!EXTILine4InterruptDMAI_StreamO_lRQn=11,*!DMAlStream0globalInterrupt*/DMAl_StreamIJRQn=12,*!DMAlStream1globalInterrupt*/DMAI_Stream2_lRQn=13,*!DMAlStream2globalInterrupt*/DMAl_Stream3RQn=14,*!DMAlStream3globalInterrupt*/DMAl_Stream4_IRQn=15,*!DMAlStream4globalInterrupt*/D
5、MAl_Stream5RQn=16,*!DMAlStream5globalInterrupt*/DMAI_Stream6RQn=,*!DMAlStream6globalInterrupt*/ADC_IRQn=18,*!ADClzADC2andADC3globalInterrupts*/CANl_TX_IRQn：19,*!CANlTXInterrupt*/CANl_RXO_IRQn=20,*!CANlRXOInterrupt*/CANl_RXl_IRQn=21,*!CANlRXlInterrupt*/CANl_SCE_IRQn=22,*!CANlSCEInterrupt*/EXTI9_5_IRQ
6、n=23,*!ExternalLine9:5Interrupts*/TIMl_BRK_TIM9_IRQn=24,*!TIMlBreakinterruptandTIM9globalinterrupt7TIMl_UP_TIM10_IRQn=25,*!TIMlUpdateInterruptandTIMlOglobalinterrupt*/TIM1_TRG_COM_TIMIlJRQn=26,*!TIMlTriggerandCommutationInterruptandTIMllglobalinterrupt*/TIMl_CC_IRQn=27,*!TIMlCaptureCompareInterrupt*
7、/TIM2JRQn=28,*!TIM2globalInterrupt*/TIM3JRQn=29,*!TIM3globalInterrupt*/TIM4JRQn=30,*!TIM4globalInterrupt*/l2Cl_EV_IRQn31,*!I2C1EventInterrupt*/l2Cl_ER_IRQn32,*!I2C1ErrorInterruptl2C2_EV_IRQn=33,*!I2C2EventInterrupt* /l2C2_ER_IRQn*/SPIlJRQn* /SPI2JRQn* /USARTl_IRQn=* /USART2_IRQn=* /USART3_IRQn=* /EX
8、TI15_10_IRQn=40,* /RTC_Alarm_IRQn=41zLineInterrupt*/OTG_FS_WKUP_IRQn=42,lineinterrupt*/TIM8_BRK_TIM12_IRQn=43,globalinterrupt*/TIM8_UP_TIM13_IRQn=44,globalinterrupt*/TIM8_TRG_COM_TIM14_IRQn=45,=34,*!I2C2ErrorInterrupt=35,*!SPIlglobalInterrupt=36,*!SPI2globalInterrupt37, *!USARTlglobalInterrupt38, /!
9、USART2globalInterrupt39, *!USART3globalInterrupt*!ExternalLine15:10Interrupts*!RTCAlarm(AandB)throughEXTI/!USBOTGFSWakeupthroughEXTI*!TIM8BreakInterruptandTIM12*!TIM8UpdateInterruptandTIM13*!TIM8TriggerandCommutationInterruptandTIM14globalinterrupt*/TIM8_CC_IRQn=46,*!TIM8CaptureCompareInterrupt*/DMA
10、l_Stream7_IRQn=47,*!DMAlStream?Interrupt*/FSMCJRQn=48,*!FSMCglobalInterrupt*/SDIOJRQn=49,*!SDIOglobalInterrupt*/TIM5JRQn=50,*!TIM5globalInterrupt*/SPI3JRQn=51,*!SPI3globalInterrupt*/ART4JRQn=52,*!UART4globalInterrupt*/UART5_IRQn=53,*!UART5globalInterrupt*/TIM6_DAC_IRQn=54,*!TIM6globalandDAC1&2underr
11、unerrorinterrupts*/TIM7JRQn=55,*!TIM7globalinterrupt*/DMA2_StreamO_IRQn=56,*!DMA2StreamOglobalInterrupt*/DMA2_Streaml_IRQn=57,*!DMA2Stream1globalInterrupt*/DMA2_Stream2_IRQn=58,*!DMA2Stream2globalInterrupt*/DMA2_Stream3_lRQn=59,*!DMA2Stream3globalInterrupt*/DMA2_Strear4IRQn=60,*!DMA2Stream4globalInt
12、errupt*/ETH_IRQn=61,*!EthernetglobalInterrupt*/ETH_WKUP_IRQn=62,*!EthernetWakeupthroughEXTIlineInterrupt*/CAN2_TX_IRQn=63,*!CAN2TXInterrupt*/CAN2_RX0_IRQn=64,*!CAN2RXOInterrupt*/CAN2_RXl_IRQn=65,*!CAN2RXlInterrupt*/CAN2_SCE_IRQn=66,*!CAN2SCEInterrupt*/OTG_FS_IRQn=67,*!USBOTGFSglobalInterrupt*/DMA2_S
13、tream5_IRQn=68z*!DMA2Stream5globalinterrupt*/DMA2_Stream6_lRQn=69,*!DMA2Stream6globalinterrupt*/DMA2_Stream7_IRQn=70,*!DMA2Stream7globalinterrupt7USART6_IRQn=71z*!USART6globalinterrupt*/l2C3_EV_IRQn=72,*!I2C3eventinterrupt*/l2C3_ER_IRQn=73,*!I2C3errorinterrupt7OTG_HS_EPl_OUT_IRQn=74,*!USBOTGHSEndPoi
14、nt1Outglobalinterrupt*/OTG_HS_EPl_IN_IRQn=75z*!USBOTGHSEndPoint1Inglobalinterrupt*/OTGHSWKUPIRQn=76,*!USBOTGHSWakeupthroughEXTIinterrupt*/=77,*!USBOTGHSglobalinterruptOTG_HS_IRQn*/DCMIJRQn=78,*!DCMIglobalinterrupt*/CRYPJRQn=79,*!CRYPcryptoglobalinterrupt*/HASH_RNG_IRQn=80,*!HashandRngglobalinterrupt
15、*/FPUJRQn=81*!FPUglobalinterrupt*/IRQn_Type;2.数据类型定义typedefint32_ts32;typedefintl6_tsl6;typedefint8_ts8;typedefconstint32_tsc32;*!ReadOnly*/typedefconstintl6_tscl6;*!ReadOnly*/typedefconstint8_tsc8;*!ReadOnly*/typedef_IOint32_tvs32;typedef_IOintl6_tvsl6;typedef_IOint8_tvs8;typedef_Iint32_tvsc32;*!Re
16、adOnly*/typedef_Iintl6_tvscl6;*!ReadOnly*/typedef_Iint8_tvsc8;*!ReadOnly*/typedefuint32_tu32;typedefuintl6_tul6;typedefuint8_tu8;typedefconstuint32_tuc32;*!ReadOnly*/typedefconstuintl6_tucl6;*!ReadOnly*/typedefconstuint8_tuc8;*!ReadOnly*/typedef_IOuint32_tvu32;typedef_IOuintl6_tvul6;typedef_IOuint8_
17、tvu8;typedef_Iuint32_tvuc32;*!ReadOnly*/typedef_Iuintl6_tvucl6;*!ReadOnly*/typedef_Iuint8_tvuc8;*!ReadOnly*/参考一下的定义typedeftypedefsignedsignedshortcharint8_t;intintl6_t;typedefsignedintint32_t;typedefsigned_int64int64_t;*exact-widthunsignedintegertypes*/typedefunsignedcharuint8_t;typedefunsignedshort
18、intuintl6_t；typedefunsignedintuint32_t;typedefunsigned_int64uint64_t;/7.18.1.2*/*smallesttypeofatleastnbits*/*minimum-widthsignedintegertypes*/typedefsignedcharint_least8_t;typedefsignedshortintint_leastl6_t;typedefsignedintint_least32_t;typedefsigned_int64int_least64_t;*minimum-widthunsignedinteger
19、types*/typedefunsignedcharuint_least8_t；typedefunsignedshortintuint_leastl6_t;typedefunsignedintuint_least32_t;typedefunsigned_int64uint_least64_t;*7.18.1.3*/*fastestminimum-widthsignedintegertypes*/typedefsignedintint_fast8_t;typedefsignedintint_fastl6_1typedefsignedintint_fast32_1typedefsigned_int
20、64int_fast64_1*fastestminimum-widthunsignedintegertypes*/typedefunsignedtypedefunsignedtypedefunsignedtypedefunsignedintuint_fast8_t;intuint_fastl6_t;intuint_fast32_t;_int64uint_fast64_t;*7.18.1.4integertypescapableofholdingobjectpointers*/typedefsignedintintptr_t;typedefunsignedintuintptr_t;*7.18.1
21、.5greatest-widthintegertypes*/typedefsigned_int64intmax_t;typedefunsigned_int64uintmax_t;3.标志状态类型定义typedefenumRESET=O,SET=!RESETFIagStatus,ITStatus;4.功能状态使能类型定义FonctionStatetypedefenumDISABLE=O,ENABLE=!DISABLEFunctionaIState;#defineIS_FUNCTIONAL_SIATE(STATE)(STATE)=DISABLE)(STATE)=ENABLE)5.ADC类型定义ty
22、pedefstruct(_IOuint32_tSR;OxOO*/_IOuint32_tCRl;0x04*/_IOuint32_tCR2;0x08*/_IOuint32_tSMPRl;OxOC*/_IOuint32_tSMPR2;OxlO*/_IOuint32_tJOFRl;*/_IOuint32_tJ0FR2;*/_IOuint32_tJ0FR3;*/_IOuint32_tJ0FR4;*/_IOuint32_tHTR;0x24*/_IOuint32_tLR;0x28*/_IOuint32_tSQRl;0x2C*/_IOuint32_tSQR2;0x30*/_IOuint32_tSQR3;0x3
23、4*/_IOuint32_tJSQR;0x38*/_IOuint32_tJDRl;*!ADCstatusregister,Addressoffset:*!ADCcontrolregister1,Addressoffset:*!ADCcontrolregister2,Addressoffset:*!ADCsampletimeregister1,Addressoffset:*!ADCsampletimeregister2,Addressoffset:*!ADCinjectedchanneldataoffsetregister1,Addressoffset:0x14*!ADCinjectedchan
24、neldataoffsetregister2,Addressoffset:0x18*!ADCinjectedchanneldataoffsetregister3,Addressoffset:OxlC*!ADCinjectedchanneldataoffsetregister4,Addressoffset:0x20*!ADCwatchdoghigherthresholdregister;Addressoffset:*!ADCwatchdoglowerthresholdregister,Addressoffset:*!ADCregularsequenceregister1,Addressoffse
25、t:*!ADCregularsequenceregister2,Addressoffset:*!ADCregularsequenceregister3zAddressoffset:*!ADCinjectedsequenceregister,Addressoffset:*!ADCinjecteddataregister1,Addressoffset:0x3C*/_IOuint32_tJDR2;0x40*/*!ADCinjecteddataregister2,Addressoffset:_IOuint32_tJDR3;0x44*/*!ADCinjecteddataregister3,Address
26、offset:_IOuint32_tJDR4;*!ADCinjecteddataregister4,Addressoffset:0x48*/_IOuint32_tDR;0x4C*/ADC_TypeDef;6.GPIO类型定义typedefstruct(*!ADCregulardataregister,Addressoffset:_IOuint32_tMODER;*!GPIOportmoderegister,Addressoffset:OxOO*/_IOuint32_tOTYPER;*/*!GPIOportoutputtyperegister,Addressoffset:0x04_IOuint3
27、2_tOSPEEDR;*!GPIOportoutputspeedregister,Addressoffset:0x08*/_IOuint32_tPUPDR;*/*!GPIOportpull-up/pull-downregister,Addressoffset:OxOC_IOuint32_tIDR;*/*!GPIOportinputdataregister,Addressoffset:OxlO_IOuint32_tODR;*/*!GPIOportoutputdataregister,Addressoffset:0x14_IOuintl6_tBSRRL;*/*!GPIOportbitset/res
28、etlowregister,Addressoffset:0x18_IOuintl6_tBSRRH;*/*!GPIOportbitset/resethighregister;Addressoffset:OxlA_IOuint32_tLCKR;*/*!GPIOportconfigurationlockregister;Addressoffset:OxlC_IOuint32_tAFR2;*!GPIOalternatefunctionregisters,Addressoffset:0x20-0x24*/GPIO_TypeDef;ZReC类型定义typedefstruct_IOuint32_tCR;*!
29、RCCclockcontrolregisteoAddressoffset:OxOO*/_IOuint32_tPLLCFGR;*!RCCPLLconfigurationregister,Addressoffset:0x04*/_IOuint32_tCFGR;*!RCCclockconfigurationregister;Addressoffset:0x08*/_IOuint32_tCIR;*!RCCclockinterruptregister,Addressoffset:OxOC*/_IOuint32_tAHBlRSTR;*!RCCAHBlperipheralresetregister;Addr
30、essoffset:OxlO*/_IOuint32_tAHB2RSTR;*!RCCAHB2peripheralresetregister,Addressoffset:0x14*/_IOuint32_tAHB3RSTR;*!RCCAHB3peripheralresetregister,Addressoffset:0x18*/uint32_t*/_IOuint32_tAPB1RSTR;RESERVEDO;*!RCCAPBl*!Reserved,peripheralresetOxlCregister,Addressoffset:0x20*/_IOuint32_tAPB2RSTR;*!RCCAPB2p
31、eripheralresetregister,Addressoffset:0x24*/uint32_tRESERVED12;*Reserved,0x28-0x2C*/_IOuint32_tAHB1ENR;*!RCCAHBlperipheralclockregister,Addressoffset:0x30*/_IOuint32_tAHB2ENR;*!RCCAHB2peripheralclockregister,Addressoffset:0x34*/_IOuint32_tAHB3ENR;*!RCCAHB3peripheralclockregister,Addressoffset:0x38*/u
32、int32_t*/_IOuint32_tAPB1ENR;RESERVED2;*!RCCAPBl*!Reserved,peripheralclockenable0x3Cregister;Addressoffset:0x40*/_IOuint32_tAPB2ENR;*!RCCAPB2peripheralclockenableregister,Addressoffset:0x44*/uint32_tRESERVED32;*!Reserved,0x48-0x4C*/_IOuint32_tAHB1LPENR;register, Address offset: 0x50 */_IO uint32_t AH
33、B2LPENR;register, Address offset: 0x54 */_IO uint32_t AHB3LPENR;register, Address offset: 0x58 */ uint32_t*/_IO uint32_t APB1LPENR;register, Address offset: 0x60 */_IO uint32_t APB2LPENR;register, Address offset: 0x64 */ uint32_t*!RCCAHBlperipheralclockenableinlowpowermode*!RCCAHB2peripheralclockena
34、bleinlowpowermode*!RCCAHB3peripheralclockenableinlowpowermodeRESERVED4;*!Reserved,0x5C*!RCCAPBlperipheralclockenableinlowpowermode*!RCCAPB2peripheralclockenableinlowpowermodeRESERVED52;*!Reserved,0x68-0x6C*/*!RCCBackup domain control register,_IOuint32_tBDCR;Addressoffset:0x70*/_IOUint32LtCSR;*!RCCc
35、lockcontrol&statusregister,Addressoffset:0x74*/uint32_tRESERVED62;*!Reserved,0x78-0x7C*/_IOuint32_tSSCGR;*!RCCspreadspectrumclockgenerationregister,Addressoffset:0x80*/_IOuint32_tPLLI2SCFGR;*!RCCPLLI2Sconfigurationregister,Addressoffset:0x84*/RCC_TypeDef;8.#define_lvolatile*!Definesreadonlypermissions*/#else#define_lvolatileconst*!Definesreadonlypermissions*/#endifftdefine_0volatile*!Defineswriteonlypermissions*/#define_IOvolatile*!Definesread/writepermissions*/
