《28335ECAN测试完整程序和实验记录.doc》由会员分享，可在线阅读，更多相关《28335ECAN测试完整程序和实验记录.doc（12页珍藏版）》请在课桌文档上搜索。
1、-. z.-. z.-DSP28335文库源代码系列1：一：说明：DSP28335 ECAN测试：声明：由于百度文库不能上传代码，故将can通讯测试程序整理到word文档，大家可以参考，并配有实验结果，只需要简单的移植既可以使用，请勿盗版！上图为参考C文件，在官方例程中都有，下面贴出重要C文件的代码。二：代码局部两个主要C文件的代码，其他C文件大家自己添加就可以了，本局部程序是AB 两个can口之间相互通讯，如果需要源代码，可以发我：letchgo163.DSP2833*_ECan：/ TI File $Revision: /main/8 $/ Checkin $Date: June 25,
2、2008 15:19:07 $/#/ FILE:DSP2833*_ECan.c/ TITLE:DSP2833* Enhanced CAN Initialization & Support Functions./#/ $TI Release: DSP2833*/DSP2823* C/C+ Header Files V1.31 $/ $Release Date: August 4, 2009 $/#include DSP2833*_Device.h / DSP2833* Headerfile Include File#include DSP2833*_E*amples.h / DSP2833* E
3、*amples Include File/-/ InitECan:/-/ This function initializes the eCAN module to a known state./void InitECan(void) InitECana();#if DSP28_ECANB InitECanb();#endif / if DSP28_ECANBvoid InitECana(void)/ Initialize eCAN-A module/* Create a shadow register structure for the CAN control registers. This
4、is needed, since only 32-bit access is allowed to these registers. 16-bit access to these registers could potentially corrupt the register contents or return false data. This is especially true while writing to/reading from a bit (or group of bits) among bits 16 - 31 */struct ECAN_REGS ECanaShadow;E
5、ALLOW;/ EALLOW enables access to protected bits/* Configure eCAN R* and T* pins for CAN operation using eCAN regs*/ ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;/配置GPIO引脚为CAN通讯 ECanaShadow.CANTIOC.bit.T*FUNC = 1; ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all; ECanaShadow.CANRIOC.all = ECanaRegs
6、.CANRIOC.all; ECanaShadow.CANRIOC.bit.R*FUNC = 1; ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;/* Configure eCAN for HECC mode - (reqd to access mailbo*es 16 thru 31) */ HECC mode also enables time-stamping feature事件抽样特征ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;CB = 1;ECanaRegs.CANMC.all = ECan
7、aShadow.CANMC.all;/* Initialize all bits of Master Control Field to zero */ Some bits of MSGCTRL register come up in an unknown state. For proper operation,/ all bits (including reserved bits) of MSGCTRL must be initialized to zero ECanaMbo*es.MBO*0.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*1.MSGCTR
8、L.all = 0*00000000; ECanaMbo*es.MBO*2.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*3.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*4.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*5.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*6.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*7.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*
9、8.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*9.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*10.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*11.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*12.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*13.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*14.MSGCTRL.all = 0*00000000; ECa
10、naMbo*es.MBO*15.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*16.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*17.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*18.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*19.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*20.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*21.MSGCTRL.all =
11、0*00000000; ECanaMbo*es.MBO*22.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*23.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*24.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*25.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*26.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*27.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*28
12、.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*29.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*30.MSGCTRL.all = 0*00000000; ECanaMbo*es.MBO*31.MSGCTRL.all = 0*00000000;/ TAn, RMPn, GIFn bits are all zero upon reset and are cleared again/as a matter of precaution.ECanaRegs.CANTA.all= 0*FFFFFFFF;/* Clear all
13、 TAn bits */ECanaRegs.CANRMP.all = 0*FFFFFFFF;/* Clear all RMPn bits */ECanaRegs.CANGIF0.all = 0*FFFFFFFF;/* Clear all interrupt flag bits */ECanaRegs.CANGIF1.all = 0*FFFFFFFF;/* Configure bit timing parameters for eCANA*/ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;ECanaShadow.CANMC.bit.CCR = 1 ; /
14、Set CCR = 1 ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; ECanaShadow.CANES.all = ECanaRegs.CANES.all; do ECanaShadow.CANES.all = ECanaRegs.CANES.all; while(ECanaShadow.CANES.bit.CCE != 1 ); / Wait for CCE bit to be set. ECanaShadow.CANBTC.all = 0; #if (CPU_FRQ_150MHZ) / CPU_FRQ_150MHz is defined in
15、DSP2833*_E*amples.h/* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps See Note at End of File */ECanaShadow.CANBTC.bit.BRPREG = 4;ECanaShadow.CANBTC.bit.TSEG2REG = 2;ECanaShadow.CANBTC.bit.TSEG1REG = 10; #endif#if (CPU_FRQ_100MHZ) / CPU_FRQ_100MHz is def
16、ined in DSP2833*_E*amples.h/* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps See Note at End of File */ ECanaShadow.CANBTC.bit.BRPREG = 4;ECanaShadow.CANBTC.bit.TSEG2REG = 1;ECanaShadow.CANBTC.bit.TSEG1REG = 6;#endif ECanaShadow.CANBTC.bit.SAM = 1; ECanaRegs.
17、CANBTC.all = ECanaShadow.CANBTC.all; ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;ECanaShadow.CANMC.bit.CCR = 0 ; / Set CCR = 0 ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; ECanaShadow.CANES.all = ECanaRegs.CANES.all; do ECanaShadow.CANES.all = ECanaRegs.CANES.all; while(ECanaShadow.CANES.bit.CCE !=
18、0 ); / Wait for CCE bit to be cleared./* Disable all Mailbo*es */ ECanaRegs.CANME.all = 0;/ Required before writing the MSGIDs EDIS;#if (DSP28_ECANB)void InitECanb(void)/ Initialize eCAN-B module/* Create a shadow register structure for the CAN control registers. This is needed, since only 32-bit ac
19、cess is allowed to these registers. 16-bit access to these registers could potentially corrupt the register contents or return false data. This is especially true while writing to/reading from a bit (or group of bits) among bits 16 - 31 */struct ECAN_REGS ECanbShadow; EALLOW;/ EALLOW enables access
20、to protected bits/* Configure eCAN R* and T* pins for CAN operation using eCAN regs*/ ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all; ECanbShadow.CANTIOC.bit.T*FUNC = 1; ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all; ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all; ECanbShadow.CANRIOC.bit.R*FUNC
21、= 1; ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all;/* Configure eCAN for HECC mode - (reqd to access mailbo*es 16 thru 31) */ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;ECanbShadow.CANMC.bit.SCB = 1;ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;/* Initialize all bits of Master Control Field to zero
22、*/ Some bits of MSGCTRL register come up in an unknown state. For proper operation,/ all bits (including reserved bits) of MSGCTRL must be initialized to zero ECanbMbo*es.MBO*0.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*1.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*2.MSGCTRL.all = 0*00000000; ECanbMbo*
23、es.MBO*3.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*4.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*5.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*6.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*7.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*8.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*9.MSGCTRL.all = 0*00000000; E
24、CanbMbo*es.MBO*10.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*11.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*12.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*13.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*14.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*15.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*16.MSGCTRL.all
25、= 0*00000000; ECanbMbo*es.MBO*17.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*18.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*19.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*20.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*21.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*22.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*
26、23.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*24.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*25.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*26.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*27.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*28.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*29.MSGCTRL.all = 0*00000000; E
27、CanbMbo*es.MBO*30.MSGCTRL.all = 0*00000000; ECanbMbo*es.MBO*31.MSGCTRL.all = 0*00000000;/ TAn, RMPn, GIFn bits are all zero upon reset and are cleared again/as a matter of precaution.ECanbRegs.CANTA.all= 0*FFFFFFFF;/* Clear all TAn bits */ECanbRegs.CANRMP.all = 0*FFFFFFFF;/* Clear all RMPn bits */EC
28、anbRegs.CANGIF0.all = 0*FFFFFFFF;/* Clear all interrupt flag bits */ECanbRegs.CANGIF1.all = 0*FFFFFFFF;/* Configure bit timing parameters for eCANB*/ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;ECanbShadow.CANMC.bit.CCR = 1 ; / Set CCR = 1 ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; ECanbShadow.CANE
29、S.all = ECanbRegs.CANES.all; do ECanbShadow.CANES.all = ECanbRegs.CANES.all; while(ECanbShadow.CANES.bit.CCE != 1 ); / Wait for CCE bit to be cleared. ECanbShadow.CANBTC.all = 0; #if (CPU_FRQ_150MHZ) / CPU_FRQ_150MHz is defined in DSP2833*_E*amples.h/* The following block for all 150 MHz SYSCLKOUT (
30、75 MHz CAN clock) - default. Bit rate = 1 Mbps See Note at end of file */ECanbShadow.CANBTC.bit.BRPREG = 4;ECanbShadow.CANBTC.bit.TSEG2REG = 2;ECanbShadow.CANBTC.bit.TSEG1REG = 10;#endif#if (CPU_FRQ_100MHZ) / CPU_FRQ_100MHz is defined in DSP2833*_E*amples.h/* The following block is only for 100 MHz
31、SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps See Note at end of file */ ECanbShadow.CANBTC.bit.BRPREG = 4;ECanbShadow.CANBTC.bit.TSEG2REG = 1;ECanbShadow.CANBTC.bit.TSEG1REG = 6;#endif ECanbShadow.CANBTC.bit.SAM = 1; ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all; ECanbShadow.CANMC.all = ECanbRegs
32、.CANMC.all;ECanbShadow.CANMC.bit.CCR = 0 ; / Set CCR = 0 ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; ECanbShadow.CANES.all = ECanbRegs.CANES.all; do ECanbShadow.CANES.all = ECanbRegs.CANES.all; while(ECanbShadow.CANES.bit.CCE != 0 ); / Wait for CCE bit to be cleared./* Disable all Mailbo*es */ ECan
33、bRegs.CANME.all = 0;/ Required before writing the MSGIDs EDIS;#endif / if DSP28_ECANB/-/ E*ample: InitECanGpio:/-/ This function initializes GPIO pins to function as eCAN pins/ Each GPIO pin can be configured as a GPIO pin or up to 3 different/ peripheral functional pins. By default all pins come up
34、 as GPIO/ inputs after reset./ Caution:/ Only one GPIO pin should be enabled for CANT*A/B operation./ Only one GPIO pin shoudl be enabled for CANR*A/B operation./ Comment out other unwanted lines.void InitECanGpio(void) InitECanaGpio(); InitECanbGpio();#if (DSP28_ECANB) InitECanbGpio();#endif / if D
35、SP28_ECANBvoid InitECanaGpio(void) EALLOW;/* Enable internal pull-up for the selected CAN pins */ Pull-ups can be enabled or disabled by the user./ This will enable the pullups for the specified pins./ Comment out other unwanted lines./GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; / Enable pull-up for GPIO30
36、(CANR*A)GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; / Enable pull-up for GPIO18 (CANR*A)/GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; / Enable pull-up for GPIO31 (CANT*A)GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; / Enable pull-up for GPIO19 (CANT*A)/* Set qualification for selected CAN pins to asynch only */ Inputs are syn
37、chronized to SYSCLKOUT by default./ This will select asynch (no qualification) for the selected pins. /GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; / Asynch qual for GPIO30 (CANR*A) GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; / Asynch qual for GPIO18 (CANR*A)/* Configure eCAN-A pins using GPIO regs*/ This specif
38、ies which of the possible GPIO pins will be eCAN functional pins./GpioCtrlRegs.GPAMU*2.bit.GPIO30 = 1;/ Configure GPIO30 for CANR*A operation GpioCtrlRegs.GPAMU*2.bit.GPIO18 = 3;/ Configure GPIO18 for CANR*A operation/GpioCtrlRegs.GPAMU*2.bit.GPIO31 = 1;/ Configure GPIO31 for CANT*A operation GpioCt
39、rlRegs.GPAMU*2.bit.GPIO19 = 3;/ Configure GPIO19 for CANT*A operation EDIS;#if (DSP28_ECANB)void InitECanbGpio(void) EALLOW;/* Enable internal pull-up for the selected CAN pins */ Pull-ups can be enabled or disabled by the user./ This will enable the pullups for the specified pins./ Comment out othe
40、r unwanted lines./GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; / Enable pull-up for GPIO8 (CANT*B)/ GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; / Enable pull-up for GPIO12 (CANT*B) GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; / Enable pull-up for GPIO16 (CANT*B)/ GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; / Enable pull-up for GPIO20
41、 (CANT*B)/GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; / Enable pull-up for GPIO10 (CANR*B)/ GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; / Enable pull-up for GPIO13 (CANR*B) GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; / Enable pull-up for GPIO17 (CANR*B)/ GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; / Enable pull-up for GPIO21 (CANR
42、*B)/* Set qualification for selected CAN pins to asynch only */ Inputs are synchronized to SYSCLKOUT by default./ This will select asynch (no qualification) for the selected pins./ Comment out other unwanted lines. / GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3; / Asynch qual for GPIO10 (CANR*B)/ GpioCtrlRe
43、gs.GPAQSEL1.bit.GPIO13 = 3; / Asynch qual for GPIO13 (CANR*B) GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; / Asynch qual for GPIO17 (CANR*B)/ GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; / Asynch qual for GPIO21 (CANR*B)/* Configure eCAN-B pins using GPIO regs*/ This specifies which of the possible GPIO pins will be eCAN functional pins./GpioCtrlRegs.GPAMU*1.bit
