实验四多周期CPU与存储器实验.doc

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1、课程名称计算机原理与设计实验名称_多周期CPU与存储器实验一、实验目的 1、深入理解MIPSCPU指令系统的功能和工作原理；2、掌握多周期CPU的工作原理和逻辑功能实现；3、熟练掌握用Verilog HDL语言设计多周期存储器的方法；4、熟练掌握对多周期存储器的仿真实验验证和硬件测试两种调试方法；5、通过对多周期CPU的运行情况进展观察和分析，进一步加深理解。二、实验要求 1、深入理解MIPSCPU指令系统的功能和工作原理；2、掌握多周期CPU的工作原理和逻辑功能实现；3、熟练掌握用Verilog HDL语言设计多周期存储器的方法；三、实验原理实现上述原理框图根据功能将其分划分为控制单元(c

2、unit)、执行单元(eunit)、指令单元(iunit)以及存储单元(munit)四大模块。 1.控制单元(cunit)是多周期微处理器的核心控制微处理器取指令、指令译码和指令执行等工作。主要由指令译码器控制器(outputs control)、算术逻辑运算控制器(ALU control)两个子模块组成。 2.执行单元(eunit)主要由存放器堆(registers)和算术逻辑单元(ALU)两个子模块组成。其中存放器是微处理器最根本的元素MIPS系统的存放器堆由32个32位存放器组成而ALU则是微处理器的主要功能部件执行加、减、比较等算术运算和与、或、或非、异或等逻辑运算。指令单元(iuni

3、t)的作用是决定下一条指令的地址PC值。 3.存储单元(munit)由存储器(memory)、指令存放器(instruction register)和存储数据存放器(memory data register)组成。四、实验容 1、设计一个32位MIPS多周期CPU具体的要求如下: 至少运行以下的6类32条MIPS指令。 1算术逻辑指令and、sub、addi 2逻辑运算指令and、0r、*or、 andi、 ori、*ori3位移指令sll、srl、sra4条件分支指令beq、bne、5无条件跳转指令j、jr 6数据传送指令lw、sw2.设计一个存储器五、实验环境与设备电脑，电箱。六、实验代

4、码设计含符号说明存放器元件代码：module regfile (rna,rnb,d,wn,we,clk,clrn,qa,qb);input4:0rna,rnb,wn;input31:0d;inputwe,clk,clrn;output31:0qa,qb;reg31:0register1:31;/r1-r31assign qa = (rna = 0) 0 : registerrna;/readassign qb = (rnb = 0) 0 : registerrnb;/readalways (posedge clk or negedge clrn) beginif (clrn = 0) beg

5、in/resetinteger i;for (i=1; i32; i=i+1)registeri = 0;endelse beginif (wn != 0) & (we = 1)/writeregisterwn = d;endendendmodule32位四选一选择器：module mu*4*32 (a0,a1,a2,a3,s,y);input 31:0a0,a1,a2,a3;input1:0s;output31:0y;function31:0select;input 31:0a0,a1,a2,a3;input 1:0s;case (s)2b00:select=a0;2b01:select=a

6、1;2b10:select=a2;2b11:select=a3;endcaseendfunctionassigny=select (a0,a1,a2,a3,s);endmodule5位二选一选择器：module mu*2*5 (a0,a1,s,y);input 4:0a0,a1;inputs;output4:0y;assigny = s a1 : a0;endmodule32位二选一选择器：module mu*2*32 (a0,a1,s,y);input 31:0a0,a1;inputs;output31:0y;assigny = s a1 : a0;endmodule存储器元件：module

7、 mcmem (clk, dataout, datain, addr, we, inclk, outclk);input31:0 datain;input31:0 addr;inputclk, we, inclk, outclk;output31:0dataout;wirewrite_enable = we & clk;lpm_ram_dqram (.data(datain),.address(addr7:2),.we(write_enable),.inclock(inclk),.outclock(outclk),.q(dataout);defparamram.lpm_width=32;def

8、param ram.lpm_widthad=6;defparamram.lpm_indata=registered;defparamram.lpm_outdata=registered;defparamram.lpm_file=mcmem.mif;defparamram.lpm_address_control=registered;endmodule控制部件：module mccu (op, func, z, clock, resetn, wpc, wir, wmem, wreg, iord, regrt, m2reg, aluc, shift, alusrca, alusrcb, pcsou

9、rce, jal, se*t, state);input5:0op, func;inputz, clock, resetn;output regwpc, wir, wmem, wreg, iord, regrt, m2reg;output reg3:0aluc;output reg1:0alusrcb, pcsource;output regshift, alusrca, jal, se*t;output reg2:0state;reg2:0ne*t_state;parameter2:0sif=3b000,/ IF statesid=3b001,/ ID statese*e=3b010,/ E

10、*E statesmem=3b011,/ MEM stateswb=3b100;/ WB statewire r_type,i_add,i_sub,i_and,i_or,i_*or,i_sll,i_srl,i_sra,i_jr;wire i_addi,i_andi,i_ori,i_*ori,i_lw,i_sw,i_beq,i_bne,i_lui,i_j,i_jal;and(r_type,op5,op4,op3,op2,op1,op0);and(i_add,r_type, func5,func4,func3,func2,func1,func0);and(i_sub,r_type, func5,f

11、unc4,func3,func2, func1,func0);and(i_and,r_type, func5,func4,func3, func2,func1,func0);and(i_or, r_type, func5,func4,func3, func2,func1, func0);and(i_*or,r_type, func5,func4,func3, func2, func1,func0);and(i_sll,r_type,func5,func4,func3,func2,func1,func0);and(i_srl,r_type,func5,func4,func3,func2, fun

12、c1,func0);and(i_sra,r_type,func5,func4,func3,func2, func1, func0);and(i_jr, r_type,func5,func4, func3,func2,func1,func0);and(i_addi,op5,op4, op3,op2,op1,op0);and(i_andi,op5,op4, op3, op2,op1,op0);and(i_ori, op5,op4, op3, op2,op1, op0);and(i_*ori,op5,op4, op3, op2, op1,op0);and(i_lw, op5,op4,op3,op2,

13、 op1, op0);and(i_sw, op5,op4, op3,op2, op1, op0);and(i_beq, op5,op4,op3, op2,op1, op0);and(i_bne, op5,op4,op3, op2,op1, op0);and(i_lui, op5,op4, op3, op2, op1, op0);and(i_j, op5,op4,op3,op2, op1,op0);and(i_jal, op5,op4,op3,op2, op1, op0);wire i_shift;or (i_shift,i_sll,i_srl,i_sra);always * begin/ co

14、ntrol signals dfault outputs:wpc=0;/do not write pcwir=0;/do not write irwmem=0;/ do not write memorywreg=0;/ do not write register fileiord=0;/ select pc as memory addressaluc=4b*000;/ ALU operation: addalusrca=0;/ ALU input a: reg a or saalusrcb=2h0;/ ALU input b: reg bregrt=0;/ reg dest no: rdm2r

15、eg=0;/ select reg cshift=0;/ select reg apcsource=2h0;/ select alu outputjal=0;/ not a jalse*t=1;/ sign e*tendcase (state)/- IF:sif: begin/ IF statewpc=1;/ write pcwir=1;/ write IRalusrca=1;/ PCalusrcb=2h1;/ 4ne*t_state=sid;/ ne*t state: IDend/- ID:sid: begin/ ID stateif (i_j) begin/ j instructionpc

16、source=2h3;/ jump addresswpc=1;/ write PCne*t_state=sif;/ ne*t state: IFendelse if (i_jal) begin/ jal instructionpcsource=2h3;/ jump addresswpc=1;/ write PCjal=1;/ reg no = 31wreg=1;/ save PC+4ne*t_state=sif;/ ne*t state: IFendelse if (i_jr) begin/ jr instructionpcsource=2h2;/ jump registerwpc=1;/ w

20、d/- MEM:smem: begin/ MEM stateiord=1;/ memory address = Cif (i_lw) beginne*t_state=swb;/ ne*t state: WBendelse begin/ storewmem=1;/ write memoryne*t_state=sif;/ ne*t state: IFendend/- WB:swb: begin/ WB stateif (i_lw)m2reg=1;/ select memory dataif (i_lw | i_addi | i_andi | i_ori | i_*ori | i_lui)regr

21、t=1;/ reg dest no: rtwreg=1;/ write register filene*t_state=sif;/ ne*t state: IFend/- ENDdefault: beginne*t_state=sif;/default stateendendcaseendalways (posedge clock or negedge resetn) begin/ state registersif (resetn = 0) beginstate=sif;endelse beginstate=ne*t_state;endendendmodule32位带使能端触发器：modul

22、e dffe32 (d,clk,clrn,e,q);input31:0d;inputclk,clrn,e;output31:0q;reg31:0q;always (negedge clrn or posedge clk)if (clrn = 0) beginq = 0;endelse beginif(e = 1)q = d;endendmodule32位触发器：module dff32 (d,clk,clrn,q);input31:0d;inputclk,clrn;output31:0q;reg31:0q;always (negedge clrn or posedge clk)if (clrn

23、 = 0) beginq = 0;endelse beginq = d;endendmoduleALU计算部件：module alu (a,b,aluc,r,z);input 31:0 a,b;input 3:0 aluc;output 31:0 r;output z;assign r = cal(a,b,aluc);assign z = |r;function 31:0 cal;input 31:0 a,b;input 3:0 aluc;case* (aluc)4b*000: cal=a+b;4b*100: cal=a-b;4b*001: cal=a&b;4b*101: cal=a|b;4b

24、*010: cal=ab;4b*110: cal=b15:0,16h0;4b*011: cal=ba4:0;4b1111: cal=$signed(b)a4:0;endcaseendfunctionendmodule其他部件：module f (reg_dest,jal,wn);input4:0reg_dest;input jal;output4:0wn;assignwn=reg_dest | 5jal;endmodulemodule sa (di,dot);input 4:0 di;output 31:0 dot;assign dot = 27b0,di;endmodulemodule ou

25、t4 (out);output 31:0 out;assign out = 32h4;endmodulemodule e (immin,se*t,immediate,offset);input15:0immin;inputse*t;output31:0 immediate,offset;wire e=se*t & immin15;wire15:0imm=16e;assignoffset =imm13:0,immin15:0,1b0,1b0;assignimmediate= imm,immin15:0;endmodulemodule bine (address,pc,add);input25:0

26、address;input3:0pc;output31:0add;assignadd=pc3:0,address25:0,1b0,1b0;endmodulemodule convert1 (dain,sain,op,func,rs,rt,rd,imm,addr);input31:0dain;output4:0sain,rs,rt,rd;output5:0op,func;output15:0imm;output25:0addr;assignsain=dain10:6;assignop=dain31:26;assignfunc=dain5:0;assignrs=dain25:21;assignrt

27、=dain20:16;assignrd=dain15:11;assignimm=dain15:0;assignaddr=dain25:0;endmodulemodule convert2 (pc,pcout);input31:0pc;output3:0pcout;assignpcout=pc31:28;endmodule七、实验检验与测试存储器的测试数据：- Copyright (C) 1991-2021 Altera Corporation- Your use of Altera Corporations design tools, logic functions - and other

28、software and tools, and its AMPP partner logic - functions, and any output files from any of the foregoing - (including device programming or simulation files), and any - associated documentation or information are e*pressly subject - to the terms and conditions of the Altera Program License - Subsc

29、ription Agreement, Altera MegaCore Function License - Agreement, or other applicable license agreement, including, - without limitation, that your use is for the sole purpose of - programming logic devices manufactured by Altera and sold by - Altera or its authorized distributors. Please refer to th

30、e - applicable agreement for further details.- Quartus II generated Memory Initialization File (.mif)DEPTH = 64;%Memory depth and width are required%WIDTH = 32;%Enter a decimal number%ADDRESS_RADI* = HE*;%Address and value radi*es are optional%DATA_RADI* = HE*;%Enter BIN, DEC, HE*, or OCT; unless%ot

31、herwise specified, radi*es = HE*%CONTENT BEGIN0.3F : 00000000;% Range-Every address from 0 to 3F = 00000000% 0 : 3c010000;% (00)main:luir1,0* address of data0% 1 : 34240080;% (04)orir4,r1,0*80* address of data0% 2 : 20050004;% (08)addir5,r0,4* counter% 3 : 0c000018;% (0c)call:jalsum* call function%

32、4 : ac820000;% (10)swr2,0(r4)* store result% 5 : 8c890000;% (14)lwr9,0(r4)* check sw% 6 : 01244022;% (18)subr8,r9,r4* sub: r8 - r9 - r4% 7 : 20050003;% (1c)addir5,r0,3* counter% 8 : 20a5ffff;% (20)loop2:addir5,r5,-1* counter - 1% 9 : 34a8ffff;% (24)orir8,r5,0*ffff* zero-e*tend: 0000ffff% A : 3908555

33、5;% (28)*orir8,r8,0*5555* zero-e*tend: 0000aaaa% B : 2021ffff;% (2c)addir9,r0,-1* sign-e*tend: ffffffff% C : 312affff;% (30)andir10,r9,0*ffff* zero-e*tend: 0000ffff% D : 01493025;% (34)orr6,r10,r9* or: ffffffff% E : 01494026;% (38)*orr8,r10,r9* *or: ffff0000% F : 01463824;% (3c)andr7,r10,r6* and: 00

34、00ffff% 10 : 10a00001;% (40)beqr5,r0,shift* if r5 = 0, goto shift% 11 : 08000008;% (44)jloop2* jumploop2% 12 : 2005ffff;% (48)shift:addir5,r0,-1* r5 = ffffffff% 13 : 000543c0;% (4c)sllr8,r5,15* 15 = ffff8000% 14 : 00084400;% (50)sllr8,r8,16* 16 = ffff8000(arith)% 16 : 000843c2;% (58)srlr8,r8,15* 15

35、= 0001ffff(logic)% 17 : 08000017;% (5c)finish: jfinish* dead loop% 18 : 00004020;% (60)sum:addr8,r0,r0* sum% 19 : 8c890000;% (64)loop:lwr9,0(r4)* load data% 1A : 20840004;% (68)addir4,r4,4* address + 4% 1B : 01094020;% (6c)addr8,r8,r9* sum% 1C : 20a5ffff;% (70)addir5,r5,-1* counter - 1% 1D : 14a0fff

36、b;% (74)bner5,r0,loop* finish% 1E : 00081000;% (78)sllr2,r8,0* move result to v0% 1F : 03e00008;% (7c)jrr31* return% 20 : 000000A3;% (80)data0% 21 : 00000027;% (84)data1% 22 : 00000079;% (88)data2% 23 : 00000115;% (8c)data3% 24 : 00000000;% (90)sum% END;六EDA阶段的实验结果编译、仿真等仿真结果如上图。八、测试数据试所需的测试数据、预期结果数据等及其相关说明输出说明：由于引脚及输出需要，故下表ir对应ir31.0且将显示高四位，pc对应pc31.0且将显示低两位，alu对应alu31.0且将显示低两位输入输出输入输出clockmem_clkpcaluirclockmem_clkpcaluir

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